1. Field of the Invention
The present invention relates to a semiconductor memory and particularly to stress applying means for applying voltage stress to word line groups more acceleratedly than a normal use at the time of screening defectiveness in a wafer state.
2. Description of the Related Art
In general, in a case where the semiconductor devices are manufactured and shipped, in order to ensure reliability, there is carried out a screening for exposing potentially defective devices and removing the defective devices to prevent the good devices from being deteriorated. As a screening method, there is often used a burn-in method which can realize both a field acceleration and temperature acceleration at the same time. In this method, the device is operated in a state that the voltage is set to be higher than the voltage to be practically used and the temperature is also set to be higher than the temperature to be practically used. In this way, stress, which is larger than the stress occurred in initial trouble under the practical use, is applied to the device for a short period of time. Then, the device, in which defectiveness of the initial operation may occur, is selected in advance before being shipped, thereby efficiently eliminating the device, in which defectiveness of the initial operation may occur, and improving reliability of the products.
In the recent DRAM, a raised voltage (for example, about 1.5.times.Vcc), is applied to a gate oxide film in a transfer gate (hereinafter called "cell transistor") of the memory cell. Due to this, a strong electrical field is applied thereto even if a film is thicker, and there occurs a problem of reliability. In the burn-in method relating to the DRAM, it is necessary to positively screen the cell transistor in which the pressurized potential voltage is applied to the gate.
Conventionally, in order to perform the screening of a cell transistor in the burn-in of the DRAM, an address scanning method is used such that a word line to be connected to the gate of the cell transistor is sequentially accessed. In this case, voltage stress is applied to the cell transistor less frequently than the case of the transistors of the peripheral circuits. Since the real time of the application of the maximum electrical field is short, a long period of time of the application of the electrical field is required in the burn-in process.
In order to solve the above-mentioned problem, one of inventors of this application proposed a semiconductor memory which can improve efficiency of stress application to the cell transistor in U.S. application No. 07/544,614. According to the above semiconductor memory, in screening defectiveness, voltage stress can be applied to all word lines of the number of word lines which is more than the number of word lines to be selected at time of the normal operation.
If the above invention is applied to the DRAM, screening of the defectiveness of the cell transistor reaches to the level where defectiveness is sufficiently settled. As a result, a bit defectiveness, which is the main defectiveness in the DRAM of 1M or that of 4M, can be settled at a high speed and efficiency of screening defectiveness can be considerably improved.
However, if there is a main factor which brings about defectiveness of reliability between word lines physically adjacent to each other in a region of a memory cell array of the semiconductor memory, there may be a case in which defectiveness of reliability between lines physically adjacent to each other cannot be screened if stress voltage is applied to all word lines at the same time in screening the defectiveness.